Digital phase-locked loop circuit for driving resonant sensors
نویسندگان
چکیده
منابع مشابه
High Speed Delay-Locked Loop for Multiple Clock Phase Generation
In this paper, a high speed delay-locked loop (DLL) architecture ispresented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which canbe triggered by double edges of the input signals. In addition, the blind zone is removed due to the elimination of reset signal. Theref...
متن کاملFuzzy logic for digital phase-locked loop filter design
The problem of robust phase-locked loop design has attracted attention for many years, particularly since the advent of the global positioning system. This paper proposes and demonstrates the use of a fuzzy PLL to estimate the time-varying phase of a sinusoidal signal. It is shown via simulation results that fuzzy PLL's offer performance comparable to analytically derived PLL's (e.g. Kalman fil...
متن کاملPhase - locked Loop Digital FM Receiver for Wireless
We investigate a non-coherent detection technique based on phase-locked loop (PLL) for wireless communication applications, with an emphasis on Digital Enhanced Cordless Telephone (DECT) system. Performance of the PLL receiver in additive white Gaussian noise (AWGN)'and interference-limited environments is simulated and compared to that of the "traditional" non-coherent receivers: limiter-discr...
متن کاملAn Efficient Cordic Processor for Complex Digital Phase Locked Loop
Volume 2, Issue 2 March – April 2013 Page 306 Abstract—Now-a-days various Digital Signal Processing systems are implemented on a platform of programmable signal processors or on application specific VLSI chips. Coordinate Rotation Digital Computer (CORDIC) algorithm has turned out to be such kind of programmable signal processor. In recent times, it has been a widely researched topic in the fie...
متن کاملAn All-Digital Phase-Locked Loop (ADPLL)-Based Clock Recovery Circuit
A new algorithm for all-digital phase-locked loops (ADPLL) with fast acquisition and large pulling range is presented in this paper. Based on the proposed algorithm, portable cell-based implementations for clock recovery with functions of a frequency synthesizer and on-chip clock generator are completed by standard cell. These modules have been designed and verified on a 0.6m CMOS process. Test...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Procedia Engineering
سال: 2010
ISSN: 1877-7058
DOI: 10.1016/j.proeng.2010.09.083